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The output buffer is an inverter with IOH =1mA @ VOH=.4V & IOL=1mA @ VOL=0.4V
It has aO/P states (0,1,Hi-Z).
The O/P buffer is designed in VLSI with the following capabilities
Custom writing service can write essays on Design Report of:Output Buffer
1. Meets IOL & VOL specs for all VDD ranges (4V-6V).
. Meets IOH & VOH specs for all VDD.
. Minimize transient power dissipation.
4. has Tf =& Tr= for CL = 50 PF.
I. Design of output inverter
PMOS transistor sizing
VS = VB=VDD= 4V (worst case for VDD & no body effect).
VD = VOH= .4V VG= 0V VTp=VTp0= -0.74 V
So, VDS= -1.6V,VGS= -4V
since VDSVDSAT= -4 +0.74 = -.66 then transistor operates in linear region.
IDS= k'(W/L)p[(VGS-VTp)VDS - VDS²/]
Wherek'= µpCOX
where COX =e0er(SiO) / TOX= (8.85410 -1)(.)/(15.510-)= .7810- F/m
Then, k'= (16010-4) COX = .564410-5 F/V.s
(W/L)p=IDS/{k'[(VGS-VTp)VDS-VDS²/]}
=1.010-/{k'[.456]}= 7.111
If we take Lp = min. Length = 0.8µ, Wp= 0.87.111= 5.6µ
So (W/L)p = 5.6/0.8
NMOS transistor sizing
VS = VB= 0V (no body effect).
VD = VOL= 0.4V VG= 4(worst case for VDD) VTn=VTn0= 0.844 V
So, VDS= 0.4V,VGS= 4V
since VDSVDSAT= 4 - 0.844 = .156 then transistor operates in linear region.
IDS= k'(W/L)n[(VGS-VTn)VDS - VDS²/]
Wherek'= µnCOX
where COX =e0er(SiO) / TOX= (8.85410 -1)(.)/(15.510-)= .7810- F/m
Then, k'= (4610-4) COX = 1.010-4 F/V.s
(W/L)n=IDS/{k'[(VGS-VTn)VDS-VDS²/]}
=1.010-/{k'[1.184]}= 8.60
If we take Ln = min. Length = 0.8µ, Wn= 0.88.60= 78.8µ
So (W/L)n = 78.8/0.8
Simulation of NMOS of output inverter
The following circuit should be used
Fig#
(File Name VOL_IOL_1.CIR)
min. VDD
VDD0 DC 4
Input Voltage
VIN 1 0
.DC VIN 0 1 0.01
NMOS Transistor
MN_A 10 0 N8 L=0.8U W=78.8U
.PLOT DC I(VIN)
.PROBE
.END
This will result in the following wave forms
See Plot #1
We see from the plot that at VOL= 0.4V we have Iout = 4.46mA which doesn't meet required IOL= 1mA
After some iterations and fine tuningwe have chosen
(W/L)n = 1/0.8
This value is simulated using the following code
(File Name VOL_IOL_.CIR)
min. VDD
VDD0 DC 4
Input Voltage
VIN 1 0
.DC VIN 0 1 0.01
NMOS Transistors
MN_A1 10 0 N8 L=0.8U W=1.5U
MN_A 10 0 N8 L=0.8U W=1.5U
MN_A 10 0 N8 L=0.8U W=1.5U
MN_A4 10 0 N8 L=0.8U W=1.5U
MN_A5 10 0 N8 L=0.8U W=1.5U
MN_A6 10 0 N8 L=0.8U W=1.5U
.PLOT DC I(VIN)
.PROBE
.END
This code will result in the following plot
See plot#
From the plot we see that at VOL = 0.4V we have Iout = 1.184mA which meets our requierment.
Simulation of PMOS of output inverter
The following circuit should be used
Fig#
(File NameVOH_IOH_1.CIR)
min. VDD
VDD0 DC 4
Gate voltage
VG0 DC 0
Input Voltage
VIN 1 0
.DC VIN 0.01
PMOS Transistor
MP_A 1P8 L=0.8U W=5.6U
.PLOT DC I(VIN)
.PROBE
.END
This will result in the following wave forms
See Plot#
We see from the plot that at VOH=.4V we have Iout =0.5mA which doesn't meet required IOL= 1mA
After some iterations and fine tuningwe have chosen
(W/L)p = 10/0.8
This value is simulated using the following code
(File Name VOH_IOH_.CIR)
min. VDD
VDD0 DC 4
Gate voltage
VG0 DC 0
Input Voltage
VIN 1 0
.DC VIN 0.01
PMOS Transistor
MP_A1 1P8 L=0.8U W=U
MP_A 1P8 L=0.8U W=U
MP_A 1P8 L=0.8U W=U
MP_A4 1P8 L=0.8U W=U
MP_A5 1P8 L=0.8U W=U
.PLOT DC I(VIN)
.PROBE
.END
This code will result in the following plot
See plot# 4
From the plot we see that at VOH = 0.4V we have Iout =1.05mA which meets our requirement.
II. Design of the NAND gate
To meet the third requirement of our design which is minimizing transient power dissipation, we should turnoff the transistors of the output inverterfast and turn them on slowly. That can be done by the manipulation of the NAND and NOR circuits used to enable and disable the output buffer.
To make NAND turns the PMOS off fast and turns it on slowly, the NAND output trip voltage should be high (i.e. NAND output signal tf slow, tr fast). Something like 0.7VDD is very good. This trip voltage should be calculated at the lowest VDD value (i.e. worst case for high trip gate).
VTRIP=(VDD+VTp+kRVTn)/(1+kR)
With VDD=4V, VTRIP=.8V, VTp=0.844V and VTp=-0.74V,
We get kR = 0.8
Where kR² =(kn/kp), kn=µnCOX(W/L)n,kp= µpCOX(W/L)p
We get 0.0568= .8875[ (W/L)n / (W/L)p ]
so , if we take (W/L)n= 1/0.8 (for both NMOS's) we get (W/L)p=50.8/0.8
This NAND is driving the gate of PMOS of the output inverter which has a capacity of
CG= COXWpLp
=(.7810-)(1010-6)(0.810-6)=0.01784 PF
Simulation of the NAND gate
Fig#4
(File Name NAND.CIR)
Test Hi-trip NAND gate
Pull up circiut
MP_A1 P8 L=0.8U W=50.8U
MP_BP8 L=0.8U W=50.8U
Pull down circuit
MN_A1 4 4 N8 L=0.8U W=U
MN_B 40 0 N8 L=0.8U W=U
Gate capacitance of PMOS of the output inverter
C_PGATE0 0.01784PF
Worst case for Hi-Vtrip,Lowest VDD
VDD0 DC 4
VIN1 1 0 PWL(0 0 N 0 5N 4 15N 4 17N 0 N 0)
VIN0 PWL(0 0 7N 0 N 4 1N 4 1N 0 N 0)
.TRAN 0.001N N
.PLOT TRAN V(1) V() V()
.PROBE
.END
The out put plot
See plot#5
From the plot we see that the NAND output trip voltage is high as the output signal tf slow, tr fast).
III. Design of the NOR gate
To meet the third requirement of our design which is minimizing transient power dissipation, we should turnoff the transistors of the output inverterfast and turn them on slowly. That can be done by the manipulation of the NAND and NOR circuits used to enable and disable the output buffer.
To make NOR turns the NMOS off fast and turns it on slowly, the NOR output trip voltage should be low (i.e. NOR output signal tf fast, tr slow). Something like 0.VDD is very good. This trip voltage should be calculated at the highest VDD value (i.e. worst case for high trip gate).
VTRIP=(VDD+VTp+kRVTn)/(1+kR)
With VDD=6V, VTRIP=1.V, VTn=0.844V and VTp=-0.74V,
We get kR =11.41
Where kR² =(kn/kp), kn=µnCOX(W/L)n,kp= µpCOX(W/L)p
We get10.446= .8875[ (W/L)n / (W/L)p ]
so , if we take (W/L)p= 1/0.8 (for both PMOS's) we get (W/L)n=45./0.8
This NOR is driving the gate of NMOS of the output inverter which has a capacity of
CG= COXWnLn
=(.7810-)(110-6)(0.810-6)=0. PF
Simulation of the NOR gate
Fig# 5
(File Name NOR.CIR)
Test Low-Trip NOR gate
Pull up circiut
MP_A 5 1 P8 L=0.8U W=U
MP_B 6 451 5 5 P8 L=0.8U W=U
Pull down circuit
MN_A 6 451 0 0 N8 L=0.8U W=45.U
MN_B 6 1 0 0 N8 L=0.8U W=45.U
Gate capacitance of PMOS of the output inverter
C_PGATE 6 0 0.PF
Worst case for low Vtrip highest VDD
VDD0 DC 4
VIN1 1 0 PWL(0 0 N 0 5N 4 15N 4 17N 0 0N 0)
VIN 451 0 PWL(0 0 7N 0 N 4 1N 4 1N 0 0N 0)
.TRAN 0.001N 0N
.PLOT TRAN V(1) V(451) V(6)
.PROBE
.END
The out put plot
See plot#6
From the plot we see that the NOR output trip voltage is LOW as the output signal tr slow, tf fast).
IV. Design ofOutput Control signalInverter
PMOS Transistor sizing
(W/L)p = (5 CL)/ (tr k'p VDD)
•we need tr = nS = 10- S
•k'p = .564410-5 F/V.S
•we take VDD = 4V (worst case)
•CL = (CG)p + (CG)n( i.e. of NAND gate)
•CGp = COXWpLp
= (.7810-) (50.810-6)(0.810-6)= .057710-14F
•CGn = COXWnLn
= (.78 10-) (.010-6)(0.810-6)= .5644810-15F
Then CL = .410710-14 F
So (W/L)p= 1.65 if we take Lp= 0.8µwe get Wp=1.= µ
NMOS Transistor sizing
(W/L)n = (5 CL)/ (tf k'n VDD)
•we need tf = nS = 10- S
•k'n = 1.010-4 F/V.S
•we take VDD = 4V (worst case)
•CL = (CG)p + (CG)n( i.e. of NAND gate)
•CGp = COXWpLp
= (.7810-) (50.810-6)(0.810-6)= .057710-14F
•CGn = COXWnLn
= (.78 10-) (.010-6)(0.810-6)= .5644810-15F
Then CL = .410710-14 F
So (W/L)n= 0.57 if we take Ln= 0.8µwe get Wn=0.46= µ
Simulation of Output Control signalInverter
Fig#6
(File Name INVERTER.CIR)
output control inverter
min. VDD
VDD0 DC 4
Input Voltage
VIN 451 0
.DC VIN 0 5 0.01
NMOS Transistor
MN_A451 0 0 N8 L=0.8U W=U
PMOS Transistor
MP_A451 P8 L=0.8U W=U
.PLOT DC V() V(451)
.PROBE
.END
The out put plot
See plot#7
V. Output BufferFull Circuit Simulation
To simulate the output buffer, a dummy voltage source and a resistor should be added to emulate the load.In addition the required capacitive load ( i.e. 50 pF) should be considered too.
To find the value of the dummy voltage source and the dummy resistor, the following system of equations should be solved
VOH - VDUM = RDUMIOH
VDUM - VOL = RDUMIOL
Which result inVDUM = .4615 VRDUM = 15.84615 Ohms
Fig # 7
(File Name OP_BUFFER.CIR)
Output Buffer
min. VDD
VDD0 DC 4
Output control voltage
VOC 451 0 PWL(0 0 N 0 5N 4 16N 4 18N 0 N 0)
Vin voltage
VIN 1 0 PWL(0 0 5N 0 7N 4 1N 4 14N 0 1N 0 0N 4 5N 4 7N 0 N 0)
.TRAN .001N N
.PLOT TRAN V(451) V(1) V(7)
.PROBE
The dummy voltage source
VDUM 8 0 DC .4615
The dummy resistor
RDUM 7 8 15.84615
Capacitive load
CL 7 0 50PF
output control inverter
NMOS Transistor
MN_INVERTER451 0 0 N8 L=0.8U W=U
PMOS Transistor
MP_INVERTER451 P8 L=0.8U W=U
NAND gate
Pull up circiut
MP_ANAND1 P8 L=0.8U W=50.8U
MP_BNANDP8 L=0.8U W=50.8U
Pull down circuit
MN_ANAND1 4 4 N8 L=0.8U W=U
MN_BNAND 40 0 N8 L=0.8U W=U
NOR gate
Pull up circiut
MP_ANOR 5 1 P8 L=0.8U W=U
MP_BNOR 6 451 5 5 P8 L=0.8U W=U
Pull down circuit
MN_ANOR 6 451 0 0 N8 L=0.8U W=45.U
MN_BNOR 6 1 0 0 N8 L=0.8U W=45.U
Output Inverter
PMOS Transistor
MP_A1 7P8 L=0.8U W=U
MP_A 7P8 L=0.8U W=U
MP_A 7P8 L=0.8U W=U
MP_A4 7P8 L=0.8U W=U
MP_A5 7P8 L=0.8U W=U
NMOS Transistors
MN_A1 7 6 0 0 N8 L=0.8U W=1.5U
MN_A 7 6 0 0 N8 L=0.8U W=1.5U
MN_A 7 6 0 0 N8 L=0.8U W=1.5U
MN_A4 7 6 0 0 N8 L=0.8U W=1.5U
MN_A5 7 6 0 0 N8 L=0.8U W=1.5U
MN_A6 7 6 0 0 N8 L=0.8U W=1.5U
.END
The out put plot
See plot#8
From the plot we find thatthat the output buffer we designed has
Tf =& Tr= for CL = 50 PF.
VI. Possible Improvements
We could also have considered
1. All junction capacitance
. Wiring capacitance
. The body effect. This will change VTp & VTn as they depend on VSB.
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